The present invention relates to electronic circuits, and, more particularly, to integrated circuit memory devices and related methods.
The continuing trend in semiconductor integrated circuits is to increase circuit density and thereby provide more circuitry in a given area. In particular, memory-intensive devices such as the personal computer have driven the need for memory circuits having increased density. Thus, it is desirable to increase the number of memory cells on a memory chip, such as a dynamic random access memory (DRAM), to provide a greater amount of memory without increasing the size of the chip. A typical DRAM includes a plurality of storage cell, each cell including an access transistor and a storage capacitor connected to the access transistor.
One approach to increase the density of a DRAM cell is to vertically stack the capacitor on the access transistor. The result is a memory cell that takes up less horizontal area and allows more memory cells to be included on a chip. In addition, the stacked arrangement can also be used with a vertical channel access transistor to reduce the size of each cell, as disclosed, for example, in U.S. Pat. No. 5,885,864 to Ma entitled xe2x80x9cMethod for Forming Compact Memory Cell Using Vertical Devices.xe2x80x9d
Unfortunately, as the area for a memory cell is decreased, the area available for the storage capacitor also decreases. Accordingly, the capacitance available to accurately store information may also be reduced. In the above mentioned patent to Ma, a cylindrical stacked storage capacitor is used to provide sufficient capacitance in a relatively small area. Unfortunately, such a stacked cylindrical capacitor and vertical channel transistor may present considerable manufacturing difficulties. In particular, the vertical channel access transistor may be difficult to make while providing a controllable and consistent channel. In addition, the cylindrical capacitor structure may also be relatively complicated and difficult to scale upward for increased capacitance.
In view of the foregoing background, it is therefore an object of the present invention to provide an integrated circuit memory device having a relatively high density, while retaining adequate capacitance levels for proper device operation.
It is a further object of the present invention to provide such a memory device that can be readily manufactured.
These and other objects, features, and advantages of the present invention are provided by an integrated circuit memory device including a substrate having at least one connection line therein and a plurality of memory cells formed on the substrate. Each memory cell includes a pillar which may be formed of epitaxial silicon. The pillar includes a lower source/drain region for the cell access transistor and which is electrically connected to the at least one connection line in the substrate. The pillar also includes an upper source/drain region for the cell access transistor, and at least one channel region extending vertically between the lower source/drain region and the upper source/drain region. The pillar may be generally cylindrical or rectangular in shape.
Each memory cell may further include at least one lower dielectric layer vertically adjacent the substrate and laterally adjacent the pillar, and at least one upper dielectric layer vertically spaced above the at least one lower dielectric layer and laterally adjacent the pillar. Also included is at least one gate for the channel of the cell access transistor between the lower and upper dielectric layers so that the vertical spacing therebetween defines a gate length for the cell access transistor. The construction of the vertical channel access transistor permits accurate control of the length of the channel. A storage capacitor is included in each memory cell adjacent to the upper source/drain region of the cell access transistor and is electrically connected thereto.
A conductive source/drain layer may be provided between the upper source/drain region of the pillar and the storage capacitor. The conductive source/drain layer has an upper surface portion and vertical sidewall portions depending therefrom. An advantageous feature of the invention is that the storage capacitor may extend adjacent to the upper surface portion and also adjacent to the vertical sidewall portions of the conductive source/drain layer to hereby provide an increased area for the storage capacitor. The conductive source/drain layer can be extended vertically relatively easily to provide a relatively high capacitance, since the vertical sidewalls can be made relatively large. This is so even as the horizontal area of each cell is scaled downward.
At least one dielectric spacer may be provided adjacent the vertical sidewall portions of the conductive source/drain layer. The storage capacitor may comprise a first electrode layer adjacent to the upper source/drain region of the pillar that is electrically connected thereto, a dielectric layer adjacent to the first electrode layer, and a second electrode layer adjacent to the dielectric layer.
In accordance with another advantageous feature of the invention, at least one electrically conductive line may be preferably intermittently connected to the at least one connection line. The connection line may be provided by a doped substrate region, and the strapping may be a metal to thus lower an effective electrical resistance of the doped substrate region.
A method aspect of the present invention is for making an integrated circuit memory device. The method includes forming at least one connection line in a substrate and forming a pillar on the connection line. The pillar includes a lower source/drain region for a cell access transistor electrically connected to the at least one connection line, an upper source/drain region for the cell access transistor, and at least one channel region extending vertically between the lower source/drain region and the upper source/drain region The method further includes forming at least one lower dielectric layer vertically adjacent to the substrate and laterally adjacent to the pillar and forming at least one upper dielectric layer vertically spaced above the at least one lower dielectric layer and laterally adjacent to the pillar. Also, at least one gate is formed for the at least one channel of the cell access transistor between the lower and upper dielectric layers so that the vertical spacing therebetween defines a gate length for the cell access transistor. Further, a capacitor is formed adjacent to the upper source/drain region of the cell access transistor and electrically connected thereto.